The present invention generally relates to programmable logic circuits, and more particularly to a programmable logic circuit which is often referred to as a field programmable gate array (FPGA).
Conventionally, semiconductor integrated circuit which has the function of realizing a desired logic circuit by interconnecting a plurality of programmable logic cells by a plurality of signal wires is known. Methods of determining the signal propagation paths within the logic circuit and the methods of determining the function to be realized by the logic cells can generally be categorized into the following two methods.
According to the first method, ON/OFF states of each switch within the signal propagation paths and functions to be realized are controlled based on data which are stored in memory cells that composes a static random access memory (SRAM). In this case, the configurations of the logic circuit which is realized are determined by the data stored in the memory cells of the SRAM, and thus, the semiconductor integrated circuit can be programmed a plurality of times.
On the other hand, according to the second method, the conductive states of fuses within the signal propagation paths are controlled, so as to determine the signal propagation paths and functions to be realized by the logic cells. In this case, the configurations of the logic circuit which is realized are determined by the conductive states of the fuses, and thus, the semiconductor integrated circuit cannot be programmed a plurality of times.
The basic structure of the logic cell can roughly be categorized into the following three kinds. According to the memory look-up table type logic cells, arbitrary functions are realized by using the inputs of the circuits as the address inputs of memories and the content of the memory cell specified by the previous memory address as the outputs of the circuits. This is done by writing the boolean truth table into the memory. According to the AND-OR plane type logic cells, arbitrary functions are realized by programming the AND plane and/or the OR plane thereof. Furthermore, according to the logic selection type logic cells, arbitrary functions are realized controlling the signal propagation paths using selection circuits such as multiplexers which can select outputs out of their applied inputs.
However, in the memory look-up table type logic cells, the number of memory cells for storing the output values increases exponentially with respect to the increase in the number of input signal wires. For this reason, the required memory capacity becomes large as the number of input signals to the logic circuit increases. Therefore, there was a problem that such programmable logic circuits comprising the memory look-up table type logic cells were difficult to realize.
In addition, in the case of the AND-OR plane type logic cells, there was a problem that complexity and redundancy of each plane became a great disturbance when forming large scale circuits.
Furthermore, in the case of the logic selection type logic cells, there was a problem that the scale of the selection circuit within the logic cell becomes large when the number of input signals to the logic circuit increases. Generally, it is known that the circuit scale of the selection circuit exponentially increases with respect to the increase in the number of input signals.
In each example of the basic architecture of the logic cell described above, the necessary number of logic cells to implement a logic circuit greatly changes when any part of any logic circuit's signal or design's logic change from positive logic to negative logic due to the modification of the logic circuit.
For this reason, there was a possibility that the mapping, a term which stands for implementing the logic circuit onto the set of logic cells, will fail if there is a modification or the like in the design specification of the logic circuit. In other words, there was a problem in that in order to reduce the circuit scale of the logic cell, an AND-OR type logic circuit is easily formed by certain set of logic cells but an OR-AND type logic circuit is difficult to form by the certain set of logic cells or vice versa.
On the other hand, the majority of the conventional logic cells have the structure shown in FIG. 1. In other words, a logic cell 100 is composed of a partial circuit 101 specialized for forming a combinational logic circuit, and a partial circuit 102 specialized for forming a sequential logic circuit, as shown in FIG. 1. The partial circuit 101 of the logic cell 100 is used when forming a combinational logic circuit, and the partial circuit 102 of the logic cell 100 is used when forming a sequential logic circuit. For this reason, if a logic circuit having a large number of combinational logic circuits is attempted to be mapped, the number of unused partial circuits 102 within this logic circuit becomes large. In addition, if a logic circuit having a large number of sequential logic circuits is attempted to be mapped, the number of unused partial circuits 101 within this logic circuit becomes large. Therefore, there was a problem that the utilization efficiency of the partial circuits 101 and 102 within the logic cell 100 becomes extremely poor depending on the structure, especially on the ratio of the combinational logic circuit part and the sequential logic circuit part within the logic circuit and the like, of the logic circuit which is to be mapped.
Unless it is known beforehand that either the combinational logic circuit or the sequential logic circuit will be used exclusively, the logic cell must be structured so that both the combinational logic and the sequential logic can be realized when forming the logic circuit. Normally, logic circuits are a combination of both a plurality of combinational logics and a plurality of sequential logics, and thus, it was necessary to provide both the partial circuit 101 and the partial circuit 102 within the logic cell 100 as shown in FIG. 1.
As a result, according to the conventional logic cell, there was a problem in that the utilization efficiency of each of the partial circuits within the logic cell, that is, the utilization efficiency of the logic cells within the logic circuit, cannot be improved regardless of the structure of the logic circuit which is to be mapped.